Track 7 Miscellaneous

A Translinear-Based Implementation of Digital Logic Gates Using Only CMOS in Current-Mode
Jitendra Singh

Design and Analysis of CMOS Ring Oscillator Using 45 nm Technology
Vandna Sikarwar, Neha Yadav and Shyam Akashe

VLIW – SIMD Processor Based Scalable Architecure for Parallel Classifier Node Computing
Venkata Ganapathi Puppala

Spectrum Sharing in Cognitive Radio Using Game Theory
Shweta Pandit and Ghanshyam Singh

Development of Optimum Addition Algorithm Using Modified Parallel Hybrid Signed Digit (MPHSD) Technique
Vishal Awasthi and Krishna Raj

Transistor Gating – Reduction of Leakage Current and Power in Full Subtractor Circuit
Milind Gautam and Shyam Akashe

A Competent Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell
Amit Dubey, Sachin Dubey and Shyam Akashe

A High Performance D-Flip Flop Design with Low Power Clocking System Using MTCMOS Technique
Paanshul Dobriyal, Karna Sharma, Manan Sethi and Geetanjali Sharma

A Low Cost Microelectromechanical Braille for Blind People to Communicate with Blind or Deaf Blind People Through SMS Subsystem
Ruman Sarkar, Smita Das and Dwijen Rudrapal

Modeling and Analysis for Single Item Multi-Attribute Reverse Auction
S. V. Nagabhushan, K. N. Subramanya and G. N. Srinivasan

A Novel Smart Card Mutual Authentication Scheme for Session Transfer Among Registered Devices
Ravi Singh Pippal, C. D. Jaidhar and Shashikala Tapaswi

Design and Analysis of Tunable Analog Circuit Using Double Gate MOSFET at 45nm CMOS Technology
Ravindra Singh Kushwah and Shyam Akashe

Quickest Path Problems in Stochastic-Flow Networks with Time Constraint – A Fast and Reliable Solution
Shivani Johari and Aparajita Ojha

Model for Drain Current Based on the Exponential Distribution of Tail States for Nanocrystalline Silicon Thin Film Transistor
Prachi Sharma and Navneet Gupta

Write Stability Analysis of 8-T Novel SRAM Cell for High Speed Application
Prashant Upadhyay, S. K. Chhotray, R. Kar, D. Mandal and S. P. Ghoshal

An Analytical Crosstalk and Delay Model for VLSI RLC Coupled Interconnects
V. Maheshwari, K. Khare, S. K. Jha, R. Kar and D. Mandal

DGS Based Microstrip Patch Antennas for UWB Systems
Rakesh Kumar Yadav, Sushrut Das and R. L. Yadava

Realization of Logic Gates Using CMOS Gilbert Multiplier Cell
Parashuram Patel

Network on Chip for DTMF Decoder and TDM Switching in Telecommunication Network with HDL Environment
Adesh Kumar, Sonal Singhal, Piyush Kuchhal and Amit Kumar

Design and Analysis of Tunable Analog Circuit Using Double Gate MOSFET at 45nm CMOS Technology
Ravindra Singh Kushwah and Shyam Akashe

Impact of Segmentation Distribution on Area and Delay in FPGA Routing Architectures
Ashish Mishra, Nidhi Jayapalan, Harsha Rastogi and Tushar Agrawal

Completion of Qualitative Spatio-Temporal Explanations Using Context
Juwesh Binong and Shyamanta M . Hazarika

A Graph Theoretic Framework for Double Patterning Lithographic Layout De-Composition
Arindam Sinharay and Tuli Bakshi

Weather-Predicting Atmospheric Modulation Transfer Function
Manvi Malik and S. Majumder

Software Change Validation Using Class Diagram and SRS
Rajat Swapnil, Aprna Tripathi and Dharmender Singh Kushwaha

Spectrum Shaping Analysis Using Tunable Parameter of Fractional Based Bartlett Window
Prabhakar Agarwal, S. P. Singh and V. K. Pandey

Development of Anthropomorphic Multi-D.O.F Master-Slave Manipulator
Sulabh Kumra, Shilpa Mehta and Ramandeep Singh

Secure Information Sharing in Digital Supply Chains
Bharat Bhargava, Rohit Ranchal and Lotfi Ben Othmane

A Low-Cost Non-Intrusive Appliance Load Monitoring System
Supratim Das, Srikrishna, Ankita Shukla, G. N. S. Harsha and Sujay Deb

AFSS Superstrate Integrated Microstrip Antennas- A Progressive Study
Sonam Thakur, R. L. Yadava and Sushrut Das

Convolutional Encoder and Viterbi Decoder Using SOPC for Variable Constraint Length
Anuradha Kulkarni, Dnyaneshwar Mantri, Neeli R. Prasad and Ramjee Prasad

Design of High Speed Hybrid Carry Select Adder
Shivani Parmar and Kirat Pal Singh